This invention relates to a picture frame generating circuit and a digital television system using the picture frame generating circuit.
In digital televisions, it is desired that multiple moving pictures are simultaneously displayed and the relative position of multiple moving pictures is instantaneously changed.
Also, it is desired that the moving picture is displayed overlapping with graphics such as a still picture and a frame is formed around the moving picture. The position of moving picture is to be optional. Also, the size of frame is to be optional.
Japanese patent application laid-open No.8-297481 (1996) discloses a graphic image display unit that a sub-image is framed when it is displayed in a main image. In this display unit, bit maps for frame and main image are stored in its memory. Referring to the memory simultaneously when scanning the image, if it corresponds to a frame then the frame is displayed, if to a main image then the main image is displayed, else a sub-image in its image memory is displayed. However, a capacity of memory equal to the image size is needed and a large amount of data renewal is needed when the position of frame, sub-image and main image is changed. Therefore, this display unit is not suitable for use in high resolution.
Japanese patent application laid-open No.6-268908 (1994) discloses a multi-image frame signal generating circuit. In this circuit, in calculating the frame when multiple images line up in the horizontal direction, the comparison of frame start point and end point in the horizontal direction and the comparison of frame start point and end point in the vertical direction are conducted. When the scan line corresponds to the start point in the horizontal direction, the coordinates of a next frame are read from its memory. When the scan line further goes on and corresponds to the coordinates of the next frame, the coordinates of a frame after the next are read from the memory. Thus, in this circuit, the position (coordinates) of frame is stored in RAM, and values stored in RAM are sequentially read to detect the position of frame. However, when the position of a moving picture is instantaneously changed, even for the framed image shifted by one pixel, it is necessary to change the four values stored in RAM. When sub-images with the same size line up in the horizontal direction, the frame positions only have to be sequentially read from the memory and compared. However, when they are deviated each other in the vertical direction or when the sizes of sub-images are different each other, it becomes impossible to frame them.
Japanese patent application laid-open No.2-082765 (1990) disclose a multi-image display control circuit. But, in this, circuit, it is not clear whether the size of frame can be set or not. From the example of the specification, it is assumed that it is fixed.
Japanese patent application laid-open No.5-204374 (1993) discloses an image display control system. Since there is no description about frame, this system simply relates to a picture-in-picture technology.
Japanese patent application laid-open No.5-346773 (1993) discloses an overlap-display control method for multiple moving pictures. In this method, display area designation memories (RM0, RM1, . . . ) are provided. Therefore, to designate a display area, amount of memory equal to the display area is required. Also, when changing the position of display image, it is necessary to rewrite a large amount of display area memory.
Japanese patent application laid-open No.10-322619 (1998) discloses an image display unit. The object of this unit is to frame the main image. In framing, it is necessary to set the position of frame. Therefore, the number of values to be set increases by that much.
Accordingly, it is an object of the invention to provide a picture frame generating circuit that the change of picture position, picture size and frame size can be achieved with less data renewal, thereby reducing the bus occupancy time in renewing data.
It is a further object of the invention to provide a digital television system that offers a quicker response speed to the TV viewer.
According to the invention, a picture frame generating circuit, comprises:
a coordinate value calculation processor that calculates frame start position (X), frame start position (Y), picture end position (X), picture end position (Y), frame end position (X) and frame end position (Y) using calculation start signal as activation signal, based on picture position (X) register, picture position (Y) register, picture size (X) register, picture size (Y) register and frame size register which are written through a data bus, the processor allowing frame color data to be written into frame color register to designate the color of frame through the data bus; and
a selection circuit of frame and picture to which the frame start position (X), the frame start position (Y), the picture end position (X), the picture end position (Y), the frame and position (X), the frame end position (Y), the picture position (X) register, picture position (Y) register, the frame color data, picture data, horizontal display position and vertical display position are input, the circuit selecting the picture data or the frame color data and outputs the selected one as display data.
According to another aspect of the invention, a digital television system, comprises:
a CPU that writes a necessary value into a register of a display unit control circuit through a data bus:
an image memory that stores picture data and frame;
the display unit control circuit that is composed of a picture frame generating circuit that switches, based on the value of the register, the picture data and frame stored in the image memory and outputs the selected one as display data; and
a display unit that displays the display data.